MAXVY MIPI CSI-2 v3 Transmitter IP

MAXVY MIPI CSI-2 Transmitter IP-V3 is licensable camera-serial-interface transmitter design IP.

It states compliance as per MIPI-CSI-2 version 3.0, with C-PHY 2.0 and D-PHY 2.5 compliance for that CSI-2 version, and CCI compatibility with I2C and I3C (SDR, DDR). Features named include pixel-to-byte conversion, continuous clock behavior for D-PHY, de-skew sequence on data lanes, lane distribution, C-PHY sync-word insertion via PPI, filler bytes for C-PHY packet footer alignment, virtual channels (16 for D-PHY, 32 for C-PHY), and data formats YUV422, RGB888/565, RAW8/10, generic 8-bit long packet, and user-defined byte data. The page states the transmitter supports C-PHY/D-PHY/A-PHY/M-PHY with only one PHY configured at a time, and AHB-Lite/APB/AXI configuration interfaces. Resource deliverables listed include Verilog source code, user/integration guides, synthesis scripts, encrypted verification test-bench, and a basic test suite. Official page is design IP (Verilog) for CSI-2 TX, not VIP.