Foundation libraries and analog IP that the rest of the SoC is built on. These are process-specific; a listing does not transfer to another foundry node by itself.
Agile Analog agileADC 12 is a 12-bit charge-redistribution SAR ADC with a stated sample rate up to 30 MSPS and a 16-channel input multiplexor for buffered or unbuffered, differential or single-ended inputs. The foundry node and the combined resolution, rate, and ENOB need confirmation. It is not a MIPI CSI-2 camera interface.
View solutionAgile Analog agileDAC 12 is a segmented current-steering DAC with a nominal 12-bit resolution and a stated rate up to 20 MSPS, in single-ended or differential form. It converts digital codes to an analog output. It is not an ADC. The process node and the operating point need confirmation.
View solutionAgile Analog agileLDO is a linear low-dropout regulator, including capless and externally biased configurations. It is not a buck converter, a switching regulator, or a finished power-management IC. The process node and the load current need confirmation.
View solutionAgile Analog agilePOK monitors a supply against programmable upper and lower thresholds, with 16 trim steps on the reviewed page. Monitoring a supply does not regulate it and does not establish complete tamper prevention.
View solutionAgile Analog agilePOR is a power-on-reset circuit with programmable normal and low-power thresholds, delays, and hysteresis. It is not a voltage regulator.
View solutionAgile Analog agileREF is a bandgap voltage reference with configurable bias outputs. It is not a clock generator and it is not a load regulator.
View solutionAgile Analog agileSensorIF is an analog sensor acquisition subsystem that combines a configurable ADC, DAC, comparator, and reference. The subsystem page states a headline rate up to 64 MSPS. That headline is not the sample rate of the standalone agileADC 12, and the independent maxima are not one simultaneous operating point. It is not a MIPI CSI-2 camera interface.
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Alphacore offers licensable high-speed low-power ADC, DAC, PLL, I/O transceiver, and SerDes PHY IP cores. The official products page publishes part-numbered tables with process nodes, rates, and product-brief downloads, stating licenses are available for validated cores.
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Aragio ESD-tolerant I/O Library IP is licensable I/O cell library IP. The official site states ownership of its IP since 2003 and lists specialty I/O including USB 2.0 PHY interface, Ethernet GMII/RGMII, and DDR pads across 65–4 nm.
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Certus Semiconductor Digital I/O libraries are licensable GPIO/ODIO/high-speed differential I/O cell libraries. The official Digital I/O page describes multi-voltage GPIO, I2C open-drain, and LVDS TX/RX offerings beyond foundry baseline IP.
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Chipus publishes a licensable analog/mixed-signal IP portfolio spanning power management, SAR ADC/DAC, oscillators, sensors, and RF front-ends with silicon-proven and GDS-available statuses across multiple foundries. The listed chipus.com/ip path failed/parked; this listing uses the official chipus-ip.com.br portfolio mirror.
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Cologne Chip C3-PLL-2 is licensable ASIC PLL IP. The official site lists ASIC IP Cores C3-PLL-2 and C3-CODEC-G712-4 alongside GateMate FPGA and telecom IC product lines.
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