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Public source

Cologne Chip C3-PLL-2 ASIC IP Core

The Cologne Chip home page reviewed on 12 November 2026 presents GateMate FPGA products and telecom ISDN transceiver IC families (XHFC/HFC), and explicitly lists ASIC IP Cores C3-PLL-2 and C3-CODEC-G712-4.

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Overview

The official site lists ASIC IP Cores C3-PLL-2 and C3-CODEC-G712-4 alongside GateMate FPGA and telecom IC product lines.

C3-PLL-2 is selected as the licensable foundation timing IP seed for ASIC integration. The company brands itself as a smart semiconductor company with distribution/quotation paths for its semiconductor products. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    PLL

  • Numbered specification: C3-PLL-2

    C3-PLL-2 is named for this product on the reviewed page.

  • Numbered specification: companion C3-CODEC-G712-4 listed

    companion C3-CODEC-G712-4 listed is named for this product on the reviewed page.

Lifecycle and categories

Solution categories
Power Management IP
Supported versions
C3-PLL-2; companion C3-CODEC-G712-4 listed
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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