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Aragio ESD-tolerant I/O Library IP

The Aragio homepage reviewed on 12 November 2026 presents ESD-tolerant I/O Library IP for package interconnect, highlighting robust ESD and latch-up immunity, fast-turnaround custom libraries, automotive qualification, and Flip-Chip/Chip & Wire compatibility.

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Overview

Nodes stated include all metal options for multiple foundries at 65/55/40/28/22/16/12/7/6/5/4 nm. Standard and specialty I/O lists include input/output/bidirectional cells, HSTL/SSTL, LVDS/SubLVDS, Mobile DDR and DDR3/4/5, PCI 3.0, LVTTL/LVCMOS, Ethernet GMII/RGMII, USB 1.1, USB 2.0 PHY Interface, NAND/Flash interface, and RF/specialized analog I/O. The company states it owns all its IP developed since 2003. Official site states owned/licensable I/O library IP portfolio.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Analog IP

    Analog or mixed-signal IP block.

  • Finder function

    I/O library

  • Numbered specification: I/O libraries across 65–4 nm nodes stated

    I/O libraries across 65–4 nm nodes stated is named for this product on the reviewed page.

  • Recorded aliases

    Aragio I/O Library; Aragio ESD I/O

Lifecycle and categories

Solution categories
Standard Cells & I/O
Supported versions
I/O libraries across 65–4 nm nodes stated
Compatibility
Flip-Chip and Chip & Wire; multi-foundry metal options 65–4 nm. Source

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