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Processor & Compute IP

RISC-V IP

RISC-V processor IP. Confirm the extensions and privilege modes the listing actually names before treating it as a drop-in core.

Showing 1–12 of 15 solutions.

  • Codasip RISC-V Processor IPCodasip logo

    RISC-V IP

    Codasip RISC-V processors are licensable, customizable RISC-V CPU IP. The official processors page states silicon-proven, RISC-V-compliant cores from embedded MCUs to application CPUs with architecture-license customization via Codasip Studio.

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  • InCore RISC-V Processor IPInCore Semiconductors logo

    RISC-V IP

    InCore publishes configurable RISC-V processor IP through an automated Core-hub generator that produces synthesizable core instances for custom semiconductor systems.

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  • Mi-V RV32 RISC-V Soft CPUMicrochip Technology logo

    RISC-V IP

    Mi-V RV32 is the RISC-V soft CPU Microchip recommends for new FPGA designs. The reviewed page lists it for PolarFire SoC, PolarFire, RTG4, SmartFusion 2, and IGLOO 2 FPGAs, with design support in Libero SoC Design Suite. Optional configuration includes compressed instructions, multiply/divide, single-precision floating point, debug, and ECC. It is processor IP for those FPGAs, not portable ASIC CPU IP, and it is not the hardened RISC-V cluster in a PolarFire SoC device.

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  • Nuclei RISC-V Processor IPNuclei System Technology logo

    RISC-V IP

    Nuclei RISC-V Processor IP is a licensable, silicon-proven RISC-V CPU IP portfolio. The official site states fully compliant architectures from ultra-low power to high-performance (Cortex-A78 equivalent class) with production-ready general-purpose, automotive, security, and AI profiles.

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  • Roa Logic RV12 RISC-V Processor IPRoa Logic logo

    RISC-V IP

    Roa Logic RV12 is licensable configurable RISC-V CPU soft IP. The official site describes a single-issue single-core RV32I/RV64I compliant processor for embedded markets, silicon-proven for FPGA and ASIC.

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  • SiFive Performance P550 Gen 3SiFive logo

    RISC-V IP

    Licensable SiFive Performance P550 Gen 3 RISC-V CPU IP for new designs. The P500 page documents embedded Linux and RTOS readiness and the RVB23 profile. Vector is not documented for this core.

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