
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
InCore Semiconductors publishes configurable RISC-V processor IP through its Core-hub generator.
Official product pages describe an automated toolchain that lets users configure ISA and microarchitecture choices and produce synthesizable RISC-V core-hub instances with interconnect, uncore and accelerator options. Named core series are presented as configurable processor IP rather than as a catalog of finished chips. InCore also publishes a related SoC Generator for integrating cores into SoC subsystems; this listing identifies the processor-IP platform and does not catalog individual core SKUs. Configuration options, ISA profiles and licensing should be confirmed on InCore's current RISC-V core pages.
ISA and microarchitecture-level configuration described by InCore
Bluespec Portable Cores are RISC-V soft processor IP offerings. The official home page lists Portable Cores (RISC-V Soft Cores), Domain-Specific Cores, and HW-Assisted Verification products, with Framingham contact details.
View solutionCloudBEAR BR-650 is licensable 64-bit RISC-V embedded CPU IP. The official product page states an in-order single-issue 8-stage pipeline optimized for low power and small area with configurable ISA extensions.
View solutionCodasip RISC-V processors are licensable, customizable RISC-V CPU IP. The official processors page states silicon-proven, RISC-V-compliant cores from embedded MCUs to application CPUs with architecture-license customization via Codasip Studio.
View solutionNOEL-V is licensable synthesizable RISC-V processor IP in GRLIB. The official page states commercial licensing for proprietary designs (fault-tolerance features excluded from the open-source GPL variant) and space/FPGA/ASIC targets.
View solutionRISC-V processor soft IP for supported Lattice FPGA designs.
View solutionMi-V RV32 is the RISC-V soft CPU Microchip recommends for new FPGA designs. The reviewed page lists it for PolarFire SoC, PolarFire, RTG4, SmartFusion 2, and IGLOO 2 FPGAs, with design support in Libero SoC Design Suite. Optional configuration includes compressed instructions, multiply/divide, single-precision floating point, debug, and ECC. It is processor IP for those FPGAs, not portable ASIC CPU IP, and it is not the hardened RISC-V cluster in a PolarFire SoC device.
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