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Public source

Frontgrade Gaisler NOEL-V RISC-V Processor IP

The NOEL-V page reviewed on 12 November 2026 describes a synthesizable VHDL RISC-V processor model that can be dual-issue, designed for space with fault-tolerant features, adopted in ASICs and flight-proven in Earth orbit.

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Overview

The official page states commercial licensing for proprietary designs (fault-tolerance features excluded from the open-source GPL variant) and space/FPGA/ASIC targets.

Architecture notes include advanced branch prediction, store-buffer cache controller, AMBA 2.0 AHB interface (optional L2/AXI4 subsystem), and standard synchronous memories. Fault tolerance includes patent-protected ECC for caches correcting single-bit and detecting multi-bit adjacent errors with optional scrubbing. Configurations tabulated include HP/GP/GP-lite/MC/MC-lite with RV32/RV64, optional MMU/PMP/hypervisor, and example software (Linux, VxWorks, RTEMS). Commercial licensing via GRLIB is stated separately from the GPL open-source version that omits fault-tolerance and high-performance FPU. Address Kungsgatan 12, 411 19 Gothenburg, Sweden is listed. Official page explicitly offers commercial licensing for proprietary NOEL-V use.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    Fault-tolerant RISC-V CPU

  • Numbered specification: RISC-V RV32/RV64 configurations HP/GP/MC (extensions per GRLIB manual)

    RISC-V RV32/RV64 configurations HP/GP/MC (extensions per GRLIB manual) is named for this product on the reviewed page.

  • Recorded aliases

    NOEL-V; Gaisler NOEL-V; GRLIB NOEL-V

Lifecycle and categories

Solution categories
RISC-V IP
Supported versions
RISC-V RV32/RV64 configurations HP/GP/MC (extensions per GRLIB manual)
Compatibility
FPGA and ASIC; AMBA AHB / optional AXI4 L2 subsystem; GRLIB plug&play. Source

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