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CloudBEAR BR-650 64-bit RISC-V Embedded Core IP

The BR-650 page reviewed on 12 November 2026 describes a 64-bit RISC-V embedded core with in-order single-issue pipeline for embedded control.

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Overview

CloudBEAR BR-650 is licensable 64-bit RISC-V embedded CPU IP. The official product page states an in-order single-issue 8-stage pipeline optimized for low power and small area with configurable ISA extensions.

Configurable ISA features listed include I/M/A/C/F/D/N/B/K/P extensions, decode/execute up to 1 instruction per cycle, Machine and User modes, 8-stage pipeline, BTB/BHT/RAS branch prediction, configurable L1 I/D-caches and TCMs with front-port TCM access, PLIC/CLINT/CLIC/NMI interrupt options, ECC (SEC-DED), Smepmp-enhanced PMP (up to 64 regions), integrated debug with HW breakpoints, compact JTAG, trace, power management, and AXI/AHB interfaces. Performance figures stated: 1.87 DMIPS/MHz and 3.73 CoreMark/MHz. Multi-core preintegrated subsystem options and tool compatibility (OpenOCD, GCC, GDB, Eclipse, IAR, SEGGER, TRACE32) are described. Official product page details synthesizable RISC-V core IP features.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    RISC-V embedded CPU

  • Numbered specification: RV64 with configurable IMA CFD N B K P extensions as listed

    RV64 with configurable IMA CFD N B K P extensions as listed is named for this product on the reviewed page.

  • Recorded aliases

    BR-650; CloudBEAR BR-650

Lifecycle and categories

Solution categories
RISC-V IP
Supported versions
RV64 with configurable IMA CFD N B K P extensions as listed
Compatibility
AXI/AHB interfaces; multi-core subsystem option; standard RISC-V toolchains. Source

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