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Public source

SiFive Intelligence X280 Gen 2

The current SiFive page identifies X280 Gen 2, 64-bit scalar and vector processing, RVV 1.0, a 512-bit vector register length, and multicore options.

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Overview

Linux-capable 64-bit RISC-V vector processor with RVV 1.0.

It is a RISC-V CPU with vector extensions, not a dedicated NPU. Silicon Showcase⁠™ reviewed the page on 2 November 2026. Pricing, license terms, process support, and the exact configuration available for a design are not stated on the reviewed page and require confirmation from the provider.

Technical capabilities

  • Published as design IP

    Licensable RISC-V processor design IP.

  • Finder function

    Linux RISC-V

  • Recorded aliases

    SiFive X280; SiFive Intelligence X280

Lifecycle and categories

Solution categories
RISC-V IP
Supported versions
RVV 1.0
Compatibility
Pricing, licensing, and configuration availability require provider confirmation. Source

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