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Nuclei RISC-V Processor IP

The Nuclei home and product pages reviewed on 12 November 2026 present a comprehensive RISC-V CPU IP portfolio.

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Overview

The official site states fully compliant architectures from ultra-low power to high-performance (Cortex-A78 equivalent class) with production-ready general-purpose, automotive, security, and AI profiles.

Marketing states Series scale performance targets and Classes meet architectural profiles, covering power-sensitive 32-bit RTOS nodes through 64-bit multicore Linux engines with AI extensions, in general-purpose and application-specific configurations. The product page enumerates N/NX/UX level families and pipeline series (200/300/600/900), including N200/N300 MCU-class cores, N600/NX600/UX600 midrange, and N900/N900 MC/UX900 MC dual-issue 9-stage application-class cores, with optional security, reliability, DSP, floating-point, vector, and NN features. Stated advantages include Verilog-based configurable cores, RISC-V B/K/P/V and user-defined instruction extensions, TEE and physical-security packages, ASIL-B/ASIL-D functional-safety packages, and CPU subsystem offerings. Home page claims industrial-grade silicon-proven IP with hundreds of customers and large unit shipments, plus open-source IDE/software stack support.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Numbered specification: B/K/P/V and custom extensions stated)

    B/K/P/V and custom extensions stated) is named for this product on the reviewed page.

  • Recorded aliases

    Nuclei RISC-V; Nuclei N900; Nuclei UX900

Lifecycle and categories

Solution categories
RISC-V IP
Supported versions
RISC-V (N/NX/UX 200–900 series; B/K/P/V and custom extensions stated)
Compatibility
Configurable CPU subsystems; TEE and ASIL packages; partner ecosystem and open-source IDE/stack stated. Source

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