
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The TTTech Chip page reviewed on 12 November 2026 states that TTTech's Chip Department provides productized silicon IP solutions and IP services to silicon and chip suppliers.
The official Chip page lists Flex IP among digital core IP building blocks with up-to-date TSN feature set and industrial automation positioning.
Under Explore IP building blocks, Flex IP is described as TSN GbE Ethernet switch / switched endpoint IP with up to 11 Gbps bandwidth (1 Gbps/100 Mbps/10 Mbps ports), TSN features 802.1Qav, 802.1Qbv, 802.1Qci, 802.1CB, and 802.1AS-2020, productized for ASIC/ASSP and FPGA integration, for industrial automation including low-latency line topologies. Related listed blocks include AS2 automotive Ethernet/TSN switch IP, ES1 Ethernet/TTE End System IP, FRS HSR/PRP switch, and prototype 10G endpoint/switch IPs. The page states IP can be used as-is, extended, or combined with third-party IP, with deliverables covering simulation, integration, and validation, and design locations including Austria. Automotive TSN Switch IP deployment claims (multi-million car shipments) appear for the broader TSN switch family.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
TSN Ethernet switch / endpoint
Numbered specification: GbE ports 1G/100M/10M
GbE ports 1G/100M/10M is named for this product on the reviewed page.
Numbered specification: up to 11 Gbps aggregate bandwidth stated
up to 11 Gbps aggregate bandwidth stated is named for this product on the reviewed page.
Algo-Logic ULL 10GE MAC + PHY is licensable ultra-low-latency 10 Gigabit Ethernet MAC/PHY soft IP for FPGA platforms. The official product page and FPGA IP Cores portfolio list IEEE 802.3-oriented MAC features with Avalon-ST/AXI4-Stream interfaces.
View solutionAtomic Rules UDP Offload Engine is licensable UDP/IPv4 FPGA IP. The official page states RFC 768/791 hardware offload for 10–400 GbE line rates with Avalon and AXI4 interfaces.
View solutionLicensable design IP. Ethernet MAC for 10 Mb/s, 100 Mb/s, and 1 Gb/s, with an external PHY.
View solutionLicensable design IP. Soft Ethernet controller for 10 Gb/s, 2.5 Gb/s, and 1 Gb/s, including MAC, PCS, and DMA functions.
View solutionChevin 10/25/40/100G MAC/PCS is licensable low-latency Ethernet MAC and PCS IP for FPGA/ASIC-oriented designs. The official page states IEEE 802.3by compliance and flexible licensing.
View solutionComcores Ethernet Controller is licensable ASIC-proven network interface IP. The official page states 10M–10GbE speeds with integrated DMA, timestamping, flexible host interfaces, and RTL deliverables.
View solution
