Arm Neoverse CMN S3
NoC IPLicensable Arm Neoverse CMN S3 coherent interconnect IP. The page documents AMBA 5 CHI and multichip support. A UCIe PHY is not included.
View solutionSecurity & Interconnect IP
NoC IP
On-chip network and coherency interconnect IP. Use this for traffic inside one die, not for the package link between dies.
Showing 1–7 of 7 solutions.
Arm Neoverse CMN S3
NoC IPArteris FlexWay Interconnect IP
NoC IP
Non-coherent network-on-chip IP for cost-efficient, low-power IoT and microcontroller SoCs.
View solutionArteris Ncore Cache Coherent Interconnect IP
NoC IPLicensable cache-coherent NoC IP. The page documents AMBA CHI and ACE. A Multi-Die option requires a separate die-to-die controller and PHY. A UCIe PHY is not included.
View solutionBaya Systems WeaveIP NoC Fabric IP
NoC IP
Baya Systems WeaveIP is chiplet-ready Network-on-Chip fabric IP for SoC and multi-chiplet systems. The official site describes a protocol-agnostic unified transport for coherent, non-coherent, and switch-fabric traffic paired with WeaverPro modeling software.
View solutionFlexGen Multi-Die NoC IP
NoC IPNewly introduced Arteris FlexGen Multi-Die NoC IP extends non-coherent network-on-chip connectivity across die-to-die links. The expanded multi-die solution is available to early access partners and strategic customers.
View solutionFlexNoC
NoC IPArteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
View solutionOPENEDGES OIC
NoC IPOPENEDGES OIC is on-chip interconnect and NoC IP. It carries SoC traffic, including traffic toward the memory controller. It is not a DDR PHY and not a memory controller.
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