
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
CMN S3 is a coherent mesh interconnect with documented multichip support.
Licensable Arm Neoverse CMN S3 coherent interconnect IP. The page documents AMBA 5 CHI and multichip support. A UCIe PHY is not included.
The die-to-die PHY and package remain separate evaluations.
Finder function
Coherent NoC
Numbered specification
AMBA 5 CHI
Configuration checks
Multichip support is documented. A UCIe PHY is not included, and this listing does not validate a combination with another vendor's die-to-die IP.
Recorded aliases
CMN S3
Non-coherent network-on-chip IP for cost-efficient, low-power IoT and microcontroller SoCs.
View solutionLicensable cache-coherent NoC IP. The page documents AMBA CHI and ACE. A Multi-Die option requires a separate die-to-die controller and PHY. A UCIe PHY is not included.
View solutionBaya Systems WeaveIP is chiplet-ready Network-on-Chip fabric IP for SoC and multi-chiplet systems. The official site describes a protocol-agnostic unified transport for coherent, non-coherent, and switch-fabric traffic paired with WeaverPro modeling software.
View solutionNewly introduced Arteris FlexGen Multi-Die NoC IP extends non-coherent network-on-chip connectivity across die-to-die links. The expanded multi-die solution is available to early access partners and strategic customers.
View solutionArteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
View solutionOPENEDGES OIC is on-chip interconnect and NoC IP. It carries SoC traffic, including traffic toward the memory controller. It is not a DDR PHY and not a memory controller.
View solution
