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OPENEDGES OIC

The OIC page describes network-on-chip IP generated through an automated RTL flow.

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Overview

OPENEDGES OIC is on-chip interconnect and NoC IP. It carries SoC traffic, including traffic toward the memory controller.

It names ActiveQoS bandwidth and latency control for the SoC memory subsystem, dynamic priority control in OIC and OMC, and a long-distance asynchronous bridge (LDA) for long routes. The page states more than 1.5 GHz at a 5nm processor, idle power under 200 µW for a backbone of more than 3 million gates, and less than 50% of the area of a typical AXI backbone. It also states end-to-end SECDED ECC and at-speed BIST. HyperPath is described as enabling 2x performance, without a stated baseline. Deliverables are IP core RTL, a simulation environment, synthesis and lint scripts, and documentation. The page does not say the interconnect is coherent, and it does not name a foundry. The 5nm figure is a clock statement on the OIC page. OMC and OPHY remain separate listings.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    on-chip interconnect

Lifecycle and categories

Lifecycle stages
NoC and interconnect
Solution categories
NoC IP
Compatibility
The OIC page describes ActiveQoS together with OMC. OIC is not a DDR controller, not a DDR PHY, and not a coherent or die-to-die interconnect. Source

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