
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
FlexGen Multi-Die is the NoC IP Arteris announced on 15 September 2026 as an expansion of its multi-die portfolio, and publishes on its FlexGen Multi-Die product page.
Newly introduced Arteris FlexGen Multi-Die NoC IP extends non-coherent network-on-chip connectivity across die-to-die links. The expanded multi-die solution is available to early access partners and strategic customers.
The product adds die-to-die controller IP to Arteris FlexGen smart NoC IP so non-coherent connectivity can cross chiplet boundaries. Arteris’s announcement states that FlexGen Multi-Die supports bidirectional transactions over a single UCIe PHY, reducing PHY area, power and I/O requirements by up to 50%, and that it includes virtual-channel link technology and quality-of-service mechanisms for shared die-to-die links. It is positioned for non-coherent AI and HPC architectures and complements Ncore Multi-Die, which remains the cache-coherent product and is not this record. The product page also describes a configurable FLIT-format die-to-die controller for third-party PHYs including UCIe and BoW, up to eight independent receive and transmit virtual channels with credited links, and application domains spanning HPC and AI accelerators for data centers, automotive, consumer and industrial electronics. This listing is distinct from FlexNoC already in the catalog.
Virtual channels and QoS across die-to-die links; FLIT-format D2D controller
Licensable Arm Neoverse CMN S3 coherent interconnect IP. The page documents AMBA 5 CHI and multichip support. A UCIe PHY is not included.
View solutionBaya Systems WeaveIP is chiplet-ready Network-on-Chip fabric IP for SoC and multi-chiplet systems. The official site describes a protocol-agnostic unified transport for coherent, non-coherent, and switch-fabric traffic paired with WeaverPro modeling software.
View solutionOPENEDGES OIC is on-chip interconnect and NoC IP. It carries SoC traffic, including traffic toward the memory controller. It is not a DDR PHY and not a memory controller.
View solutionNon-coherent network-on-chip IP for cost-efficient, low-power IoT and microcontroller SoCs.
View solutionLicensable cache-coherent NoC IP. The page documents AMBA CHI and ACE. A Multi-Die option requires a separate die-to-die controller and PHY. A UCIe PHY is not included.
View solutionArteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
View solution

