
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Baya Systems home/products content reviewed on 12 November 2026 positions a unified, software-defined approach to scalable NoC fabrics for modern SoCs and chiplet systems.
WeaveIP Advanced System IP is described as high-performance, chiplet-ready fabrics with a unified transport architecture that is protocol-agnostic and scalable, supporting coherent, non-coherent, and switch fabric communication optimized for performance, efficiency, and silicon footprint. Companion WeaverPro is described as foundational software to model, analyze, and optimize system architectures with real workloads before implementation. Target segments named include data center, infrastructure, AI acceleration, automotive, and IoT. Office locations listed include Santa Clara, Austin, Cambridge, and Bengaluru, with Santa Clara, CA 95054, USA called out. Partnership news items reference semiconductor IP availability expansion but do not replace the WeaveIP product description above. Official site clearly presents WeaveIP as advanced system NoC fabric IP for licensing/engagement.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
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Chiplet-ready NoC fabric
Numbered specification: versions not enumerated on page)
versions not enumerated on page) is named for this product on the reviewed page.
Recorded aliases
WeaveIP; Baya WeaveIP; Baya Systems NoC
Licensable Arm Neoverse CMN S3 coherent interconnect IP. The page documents AMBA 5 CHI and multichip support. A UCIe PHY is not included.
View solutionNon-coherent network-on-chip IP for cost-efficient, low-power IoT and microcontroller SoCs.
View solutionLicensable cache-coherent NoC IP. The page documents AMBA CHI and ACE. A Multi-Die option requires a separate die-to-die controller and PHY. A UCIe PHY is not included.
View solutionNewly introduced Arteris FlexGen Multi-Die NoC IP extends non-coherent network-on-chip connectivity across die-to-die links. The expanded multi-die solution is available to early access partners and strategic customers.
View solutionArteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
View solutionOPENEDGES OIC is on-chip interconnect and NoC IP. It carries SoC traffic, including traffic toward the memory controller. It is not a DDR PHY and not a memory controller.
View solution
