
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
MosChip’s silicon design services page documents RTL-to-GDSII implementation, including place and route, multi-corner static timing analysis, and sign-off.
The turnkey ASIC page adds package, assembly, ATE testing, and qualification, and says fabrication and packaging are coordinated with foundry and OSAT partners. Architecture or RTL that a customer already owns is not assumed to be part of the engagement.
Design service
Silicon engineering services. This record is not an imec listing and not licensable IP.
Availability
Listed by the provider. Confirm the configuration before use.
Configuration checks
Confirm scope, project deliverables, third-party IP rights, foundry, package, verification, and production responsibilities.
Recorded aliases
turnkey ASIC; RTL to GDS; silicon engineering
Workstream physical-design
The silicon design services page documents synthesis, DFT, and physical implementation, including place and route.
Workstream signoff
The silicon design services page documents multi-corner static timing analysis and place and route through sign-off, plus DFT sign-off. Analog layout on that page includes DRC and LVS sign-off.
Workstream packaging
The turnkey ASIC page lists package and assembly, and says fabrication and packaging are coordinated with foundry and OSAT partners. MosChip describes single-point accountability for that engagement. The page does not say MosChip operates the assembly house.
Workstream test-development
The silicon design services page documents scan insertion, ATPG, MBIST, and DFT sign-off. That is test design during implementation, not production test.
Workstream qualification
The turnkey ASIC page lists qualification and release to production. The standard and the lab are not named.
Workstream url physical-design
https://moschip.com/silicon-engineering-services/silicon-design-services/
Workstream url signoff
https://moschip.com/silicon-engineering-services/silicon-design-services/
Workstream url packaging
https://moschip.com/silicon-engineering-services/turnkey-asic-development/
Workstream url test-development
https://moschip.com/silicon-engineering-services/silicon-design-services/
Workstream url production-test
https://moschip.com/silicon-engineering-services/turnkey-asic-development/
Workstream url qualification
https://moschip.com/silicon-engineering-services/turnkey-asic-development/
Engagement model
turnkey. The turnkey page describes end-to-end ownership and single-point accountability across design, foundry, and OSAT partners.
GUC APT is a 2.5D/3D multi-die ASIC packaging-design platform, not a foundry process node and not OSAT assembly.
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