CPU, GPU, DSP, NPU, RISC-V and custom accelerators.
BrainChip Akida is licensable neuromorphic neural processor IP. The official IP page describes Akida 1, Akida Pico, and Akida 2 variants with event-based acceleration and IP brochure downloads.
View solutionLicensable design IP. H.264 Constrained Baseline encoder with a compressed reference-frame store.
View solutionLicensable H.264 Constrained Baseline decoder IP. It decodes that profile and is not an encoder. Latency, resolution, and frame rate need confirmation.
View solutionLicensable H.264 Constrained Baseline encoder IP for a low-power streaming path. Profile, resolution, frame rate, and bandwidth need confirmation. It is a different core from H.264-E-CFS and it is not a decoder.
View solutionLicensable baseline JPEG and Motion-JPEG encoder IP, 8-bit samples, with AXI Streaming and an APB control interface. It is not JPEG XL, not an image signal processor, and not an H.264 codec.
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CEVA-NeuPro-Nano is edge NPU processor IP, not a discrete accelerator chip and not a full SoC.
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A published family of embedded AI processor IP for integration into chips.
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Chips&Media WAVE video codec IP is a licensable encoder/decoder/codec lineup. The official English products page states WAVE6/WAVE5 and JPEG/CODA series supporting various media formats with competitive PPA.
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CloudBEAR BR-650 is licensable 64-bit RISC-V embedded CPU IP. The official product page states an in-order single-issue 8-stage pipeline optimized for low power and small area with configurable ISA extensions.
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Codasip RISC-V processors are licensable, customizable RISC-V CPU IP. The official processors page states silicon-proven, RISC-V-compliant cores from embedded MCUs to application CPUs with architecture-license customization via Codasip Studio.
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Crucial IP licenses video and display processing silicon IP cores for ASIC and FPGA. Official home and About pages state source-code licensing, FPGA evaluation options, and focus on image-quality processing cores for consumer/broadcast markets.
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EdgeCortix DNA-II is licensable neural network IP for ASIC, FPGA or SoC. The official DNA page describes run-time reconfigurable interconnects, scalable performance from 1K MACs, and MERA software co-optimization.
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