
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
CAST documents an H.264 Constrained Baseline encoder.
Its compressed frame store avoids external DRAM for that encoder's reference frames. That claim does not remove DRAM from the rest of a camera SoC. This is a video encoder, not an image signal processor and not a CSI-2 controller. Silicon Showcase™ reviewed the page on 2 November 2026. Pricing, license terms, process support, and the exact configuration available for a design are not stated on the reviewed page and require confirmation from the provider.
Published as design IP
Licensable H.264 encoder design IP.
Finder function
video encoder
Allegro DVT licenses hardware video encoder and decoder RTL IP covering H.264/HEVC/VP9/AV1/VVC/JPEG and related formats. Official home and Prism E300 Encoder pages state multi-format architectures with RTL source deliverables and AMBA interfaces.
View solutionAlma JPEG-E is licensable Baseline JPEG encoder IP. The official page states ISO/IEC 10918-1 Baseline Sequential DCT compliance with ASIC RTL or FPGA netlist deliverables.
View solutionAtria Logic H.264 UHD Hi422 Intra Encoder is licensable video codec IP. The official site lists High Quality, Low Latency UHD Hi422 60 fps Intra H.264 Codec IP among its multimedia products.
View solutionBitSim FPGA IP Blocks are licensable/reusable imaging and data-acquisition soft IP. The official site states IP blocks for video, graphics, big data, and data acquisition for detector, sensor-interface, and camera products.
View solutionLicensable H.264 Constrained Baseline decoder IP. It decodes that profile and is not an encoder. Latency, resolution, and frame rate need confirmation.
View solutionLicensable H.264 Constrained Baseline encoder IP for a low-power streaming path. Profile, resolution, frame rate, and bandwidth need confirmation. It is a different core from H.264-E-CFS and it is not a decoder.
View solution
