
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Crucial IP home page reviewed on 12 November 2026 titles Silicon IP for Video and Display Processing and states Crucial IP Inc. is a provider of silicon IP and design services to the Consumer Electronics and Broadcast industries, committed to high-quality, cost-effective IP cores for ASIC and FPGA with focus on image quality and robust design.
Partner callouts include Altera Megafunction Partners Program (AMPP) and Xilinx Alliance Program membership. The About page states the company is based in Toronto, founded by veterans with over 60 years combined experience in consumer video and computer graphics; cores undergo hundreds of hours of testing; silicon IP cores are available for licensing at the source-code level; customization and full custom design services are offered; and video cores are available for evaluation on off-the-shelf FPGA kits and/or time-limited trials. Same-domain product briefs for CXC-1 cross converter and VPC-4 rotator describe parameterized deinterlace/scale/rotation IP with Verilog source and testbench under license. Candidate country South Korea is superseded by Toronto, Canada on the About page. Individual core datasheet HTML pages were not separately published beyond PDF briefs. Official site confirms source-licensed video/display silicon IP for ASIC/FPGA; city/country corrected from About page.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Numbered specification: VPC-4 rotator) for ASIC/FPGA as described in site/PDF briefs
VPC-4 rotator) for ASIC/FPGA as described in site/PDF briefs is named for this product on the reviewed page.
Allegro DVT licenses hardware video encoder and decoder RTL IP covering H.264/HEVC/VP9/AV1/VVC/JPEG and related formats. Official home and Prism E300 Encoder pages state multi-format architectures with RTL source deliverables and AMBA interfaces.
View solutionAlma JPEG-E is licensable Baseline JPEG encoder IP. The official page states ISO/IEC 10918-1 Baseline Sequential DCT compliance with ASIC RTL or FPGA netlist deliverables.
View solutionAtria Logic H.264 UHD Hi422 Intra Encoder is licensable video codec IP. The official site lists High Quality, Low Latency UHD Hi422 60 fps Intra H.264 Codec IP among its multimedia products.
View solutionBitSim FPGA IP Blocks are licensable/reusable imaging and data-acquisition soft IP. The official site states IP blocks for video, graphics, big data, and data acquisition for detector, sensor-interface, and camera products.
View solutionLicensable design IP. H.264 Constrained Baseline encoder with a compressed reference-frame store.
View solutionLicensable H.264 Constrained Baseline decoder IP. It decodes that profile and is not an encoder. Latency, resolution, and frame rate need confirmation.
View solution
