
SC26
- November 15 – 20, 2026
- Chicago, Illinois, USA
- Organized by SC Conference Series
Public source
Micron high-bandwidth memory is a publicly described stacked DRAM technology for high-performance computing.
Official Micron pages present HBM as vertically stacked DRAM dies connected with high-density interconnects, including through-silicon vias, to increase memory bandwidth and improve power efficiency versus conventional DRAM in the same class of systems. Named generations including HBM3E and HBM4 remain successive implementations of this HBM family rather than separate listings. Micron positions the technology for AI and data-center computing platforms rather than as a consumer memory module. Product-generation names, capacity options and interface details should be taken from Micron's current HBM documentation.
TSV-based die interconnect
Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is one licensable multi-protocol host controller. The page says it supports SD 3.0, SDIO 3.0, and eMMC 5.1. Search under eMMC, SD, or SDIO resolves to this same listing.
View solutionArasan UFS 2.1 Host Controller IP is licensable UFS host controller IP. The page describes an M-PHY adapter layer and a UniPro link layer. The physical M-PHY is a separate offering.
View solutionLicensable standalone last-level cache IP for a non-coherent AXI4 interface. It is not a cache-coherent NoC, not a DDR controller, and not an OTP.
View solutionAttopsemi I-fuse is licensable OTP memory IP based on a non-explosive fuse programming mechanism. The official technology page states foundry-independent OTP without extra masks and physics-based electro-migration programming.
View solutionLicensable design IP. DDR and LPDDR controller for LPDDR5, LPDDR4X, LPDDR4, LPDDR3, DDR5, DDR4, DDR3L, and DDR3.
View solutionLicensable design IP. LPDDR5 and LPDDR4X PHY for a documented TSMC N7 variant. The controller is separate.
View solution