
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
P670 remains a separate listing from the P650 scalar core.
Licensable SiFive Performance P670 RISC-V vector application CPU IP. The P600 page documents a thirteen-stage, four-issue, out-of-order pipeline, RVA22, Vector 1.0, and Linux for these 64-bit application processors.
Linux is documented as an operating-system stack for the P600-series 64-bit application processors. Confirm the package for this core.
Finder function
Linux RISC-V
Numbered specification
RVA22; RVV 1.0
Configuration checks
Linux is documented for the P600-series application processors that include P670. Confirm the software package for this core. A mobile OS claim is not documented on the P600 page.
Recorded aliases
P670
Bluespec Portable Cores are RISC-V soft processor IP offerings. The official home page lists Portable Cores (RISC-V Soft Cores), Domain-Specific Cores, and HW-Assisted Verification products, with Framingham contact details.
View solutionCloudBEAR BR-650 is licensable 64-bit RISC-V embedded CPU IP. The official product page states an in-order single-issue 8-stage pipeline optimized for low power and small area with configurable ISA extensions.
View solutionCodasip RISC-V processors are licensable, customizable RISC-V CPU IP. The official processors page states silicon-proven, RISC-V-compliant cores from embedded MCUs to application CPUs with architecture-license customization via Codasip Studio.
View solutionNOEL-V is licensable synthesizable RISC-V processor IP in GRLIB. The official page states commercial licensing for proprietary designs (fault-tolerance features excluded from the open-source GPL variant) and space/FPGA/ASIC targets.
View solutionInCore publishes configurable RISC-V processor IP through an automated Core-hub generator that produces synthesizable core instances for custom semiconductor systems.
View solutionRISC-V processor soft IP for supported Lattice FPGA designs.
View solution
