
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Trilinear DisplayPort Transmitter product page reviewed on 12 November 2026 describes a 5th-generation DisplayPort Transmitter Link Controller core supporting DisplayPort 1.4–2.1 and embedded DisplayPort 1.5, including link rates up to 20 Gbps, Display Stream Compression (DSC 1.2), multi-stream transport (MST), and HDCP 1.3/2.2/2.3.
The base core includes Main Link, Secondary Channel, and AUX Channel protocols. Stated features include 1/2/4 pixels per input cycle up to 16K resolution, SST or MST operation, deep color/HDR, DSC transport with FEC support, and interfaces to external third-party PHYs for ASICs from 7 nm to 65 nm plus FPGA implementations. The page states silicon provenance on multiple ASIC and FPGA processes. Confirm the exact revision, role, and deliverables on the current provider page before integration.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
DisplayPort transmitter controller
Numbered specification: DisplayPort 2.1 / 1.4a
DisplayPort 2.1 / 1.4a is named for this product on the reviewed page.
Numbered specification: embedded DisplayPort 1.5
embedded DisplayPort 1.5 is named for this product on the reviewed page.
Numbered specification: DSC 1.2
DSC 1.2 is named for this product on the reviewed page.
Numbered specification: HDCP 1.3/2.2/2.3
HDCP 1.3/2.2/2.3 is named for this product on the reviewed page.
Recorded aliases
Trilinear DP TX; Trilinear DisplayPort Transmitter
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