
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Tetrivis home page reviewed on 12 November 2026 describes analogue, mixed-signal, and RF ASIC design and IP development.
Under Tetrivis Semiconductors, the IP portfolio is stated to include silicon-proven Tx/Rx RFICs, ADCs, CLK-PLLs, RF-PLLs, and DACs, with KuKa Ku-band and Ka-band mmWave ICs aimed at LEOSAT/global internet access. Consulting services cover DC to 81 GHz in Bipolar/BiCMOS/CMOS from 0.5 µm to 22 nm. News references joint development of a UCIe-based 12 nm Ku/Ka-band RF chiplet transceiver with Analogue Insight. Confirm the exact revision, role, and deliverables on the current provider page before integration.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Finder function
RF transceiver / ADC / PLL
Recorded aliases
Tetrivis KuKa; Tetrivis RF IP
Agile Analog agileLDO is a linear low-dropout regulator, including capless and externally biased configurations. It is not a buck converter, a switching regulator, or a finished power-management IC. The process node and the load current need confirmation.
View solutionAgile Analog agilePOK monitors a supply against programmable upper and lower thresholds, with 16 trim steps on the reviewed page. Monitoring a supply does not regulate it and does not establish complete tamper prevention.
View solutionAgile Analog agilePOR is a power-on-reset circuit with programmable normal and low-power thresholds, delays, and hysteresis. It is not a voltage regulator.
View solutionAgile Analog agileREF is a bandgap voltage reference with configurable bias outputs. It is not a clock generator and it is not a load regulator.
View solutionCologne Chip C3-PLL-2 is licensable ASIC PLL IP. The official site lists ASIC IP Cores C3-PLL-2 and C3-CODEC-G712-4 alongside GateMate FPGA and telecom IC product lines.
View solutionDolphin Semiconductor power management IP is a licensable platform of LDO, DC/DC, SIMO, ABB, and voltage-monitor blocks. The official page states nano-power designs across process nodes and a per-project licensing model.
View solution
