Discover 169 technologies from leading innovators around the world.
GUC APT is a 2.5D/3D multi-die ASIC packaging-design platform, not a foundry process node and not OSAT assembly.
AI & HPCData CenterTelecommunicationsView Technology
Powerchip 3D AI Foundry is a wafer-on-wafer logic/memory stacking foundry offering, parked in Advanced Packaging because Foundry / Process does not yet exist.
AutomotiveAI & HPCData CenterView Technology
Vanguard BCD, UHV and SOI are specialty foundry process platforms for power management, parked in Power pending Foundry / Process.
AutomotiveIndustrialConsumer Electronics+1View Technology
Realtek Ethernet Total Solutions is a wired-connectivity PHY and controller platform, currently evidenced by live 2.5GbE product pages.
Data CenterConsumer ElectronicsTelecommunications+1
GlobalWafers Silicon Wafers are the company's silicon starting substrates, including annealed, epitaxial, SOI and diffusion wafers.
AutomotiveAI & HPCIndustrial+1View Technology
Alchip’s 2nm Design Platform is an ASIC physical-design methodology for 2nm compute dies and chiplet packaging, not a foundry process node.
AI & HPCData CenterTelecommunicationsView Technology
eMemory NeoFuse is anti-fuse embedded OTP/PMTP silicon IP for logic process nodes, not a discrete memory product.
AutomotiveAI & HPCConsumer Electronics+1View Technology
UMC 22ULP/ULL is the foundry’s 22-nanometer ultra-low-power / ultra-low-leakage logic process platform.
AutomotiveConsumer ElectronicsTelecommunications+1View Technology
Nanya’s second-generation 10nm-class DRAM is the company’s current DRAM process generation, described in official investor communications.
AutomotiveData CenterConsumer ElectronicsView Technology
ASE VIPack is ASE’s heterogeneous-integration packaging platform for high-density chiplet and advanced-package construction.
AI & HPCData CenterConsumer Electronics+1
Filogic is MediaTek’s Wi-Fi 6/6E/7 connectivity platform for routers, gateways, access points and clients, with Multi-Link Operation, 320 MHz channels, 4096-QAM and dedicated NPUs on flagship access-point chips.
Consumer ElectronicsTelecommunicationsIoTView Technology
TSMC InFO is a wafer-level integrated fan-out packaging platform using high-density redistribution layers for mobile, network and high-performance computing integration.
AI & HPCConsumer ElectronicsTelecommunicationsView Technology
TSMC-SoIC is a wafer-level frontend 3D chip-stacking platform for homogeneous and heterogeneous chiplets, distinct from CoWoS 2.5D packaging and InFO fan-out.
AI & HPCData CenterView Technology
TSMC CoWoS is a 2.5D advanced packaging platform that integrates logic dies and high-bandwidth memory on an interposer for high-performance computing and AI systems.
AI & HPCData CenterView Technology
TSMC umbrella family of 3D silicon stacking and advanced packaging. CoWoS, TSMC-SoIC and InFO are constituent platforms listed separately.
AI & HPCData CenterView Technology
