WAFER-LEVEL INTEGRATED FAN-OUT
Wafer-level integrated fan-out with high-density redistribution layers
Wafer-level integrated fan-out with high-density redistribution layers
Through-InFO vias for vertical interconnect
AI & HPC · Consumer Electronics · Telecommunications
Public source
TSMC InFO is a publicly named wafer-level integrated fan-out packaging platform.
Silicon Showcase illustrative visual
Illustrative representation based on publicly available technical information.
TSMC InFO is a wafer-level integrated fan-out packaging platform using high-density redistribution layers for mobile, network and high-performance computing integration.
Official TSMC pages describe high-density redistribution layers and through-InFO vias used to integrate dies for mobile and high-performance computing, with high-volume shipments described since 2016. Named constructions such as InFO-PoP for mobile application processors with DRAM and InFO-oS for multi-chiplet logic remain capabilities of this platform rather than separate listings. InFO is a constituent of the 3DFabric family and is distinct from CoWoS 2.5D interposer packaging and from TSMC-SoIC frontend stacking. Design rules and current service options should be confirmed on TSMC’s InFO pages.
Key characteristics associated with this technology.
Wafer-level integrated fan-out with high-density redistribution layers
Through-InFO vias for vertical interconnect
InFO-PoP and InFO-oS constructions as platform capabilities, not separate listings
Constituent of TSMC 3DFabric, distinct from CoWoS and TSMC-SoIC
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