WAFER-LEVEL FRONTEND 3D
Wafer-level frontend 3D chip stacking for homogeneous and heterogeneous chiplets
Wafer-level frontend 3D chip stacking for homogeneous and heterogeneous chiplets
Chip-on-wafer and wafer-on-wafer schemes as platform capabilities
AI & HPC · Data Center
Public source
TSMC-SoIC is TSMC’s publicly named wafer-level frontend 3D stacking platform for re-integrating chiplets into a compact stacked chip.
Silicon Showcase illustrative visual
Illustrative representation based on publicly available technical information.
TSMC-SoIC is a wafer-level frontend 3D chip-stacking platform for homogeneous and heterogeneous chiplets, distinct from CoWoS 2.5D packaging and InFO fan-out.
Official TSMC 3DFabric pages describe SoIC as a high-density bonding service that can later be assembled with conventional packages or with backend 3DFabric services such as CoWoS. Chip-on-wafer and wafer-on-wafer schemes are described as capabilities of this platform, not as independent listings. SoIC is grouped under the 3DFabric family and is distinct from CoWoS 2.5D interposer packaging and from InFO fan-out. Bonding pitches, node compatibility and service options should be confirmed on TSMC’s SoIC pages.
Key characteristics associated with this technology.
Wafer-level frontend 3D chip stacking for homogeneous and heterogeneous chiplets
Chip-on-wafer and wafer-on-wafer schemes as platform capabilities
Can be assembled with conventional packages or with CoWoS backend services
Constituent of TSMC 3DFabric, distinct from CoWoS and InFO
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