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2.5D chip-on-wafer-on-substrate integration of logic and HBM
2.5D chip-on-wafer-on-substrate integration of logic and HBM
Silicon, RDL and local-silicon-interconnect interposer options as platform capabilities
AI & HPC · Data Center
Public source
TSMC CoWoS is a publicly named 2.5D advanced packaging platform that places logic dies and high-bandwidth memory on an interposer for high-performance computing and AI products.
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Illustrative representation based on publicly available technical information.
TSMC CoWoS is a 2.5D advanced packaging platform that integrates logic dies and high-bandwidth memory on an interposer for high-performance computing and AI systems.
Official TSMC pages describe Chip-on-Wafer-on-Substrate as a wafer-level integration service in volume production since 2012. Named interposer options include silicon (CoWoS-S), redistribution-layer (CoWoS-R) and local-silicon-interconnect (CoWoS-L) constructions; those remain capabilities of this platform rather than separate listings. CoWoS is a constituent of the 3DFabric family and is distinct from TSMC-SoIC frontend stacking and InFO fan-out. Interposer sizes, design rules and current service options should be confirmed on TSMC’s CoWoS pages.
Key characteristics associated with this technology.
2.5D chip-on-wafer-on-substrate integration of logic and HBM
Silicon, RDL and local-silicon-interconnect interposer options as platform capabilities
Described for high-performance computing and AI products
Constituent of TSMC 3DFabric, distinct from TSMC-SoIC and InFO
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