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Syntacore SCR RISC-V Processor IP

The RISC-V Core IP products page reviewed on 12 November 2026 describes Syntacore’s SCR portfolio as configurable SystemVerilog IP supplied with software development toolkit, FPGA-based SDK, and documentation.

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Overview

Application-class cores listed include SCR5 (efficient Linux-capable 9-stage in-order, MMU, L1/L2, coherency; SMP up to 4), SCR7 (12-stage dual-issue out-of-order; SMP up to 8), and SCR9 (12-stage dual-issue out-of-order with VPU, coherency, hypervisor; SMP up to 16), with stated 32/64-bit and up to 2 GHz+ multicore configurations. Microcontroller-class cores include open-source SCR1 (4-stage compact MCU), SCR3 (5-stage with privilege modes, MPU, L1/L2), and SCR4. The home page states ten basic silicon-proven customizable cores from entry-level MCU to entry-level server-class, with pre-built toolchains, IDEs, OS, bootloaders, and runtimes. Markets named include IoT, industrial, storage, embedded, telecom, AI/ML, enterprise, PC/laptops, and networking. Official products page lists concrete SCR SKUs with pipeline/SMP features as licensable RISC-V IP.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    RISC-V CPU

  • Recorded aliases

    Syntacore SCR; SCR5; SCR7; SCR9; SCR1

Lifecycle and categories

Solution categories
RISC-V IP
Supported versions
RISC-V SCR1/3/4/5/7/9 family (MCU to Linux application-class; SMP/coherency/VPU/hypervisor per SKU)
Compatibility
SystemVerilog deliverables; FPGA SDK and full software stack stated. Source

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