Discover 169 technologies from leading innovators around the world.
QuickLogic Australis is embedded FPGA IP, not a standalone FPGA chip and not a foundry process.
AI & HPCIndustrialAerospace & Defense+1View Technology
CEVA-NeuPro-Nano is edge NPU processor IP, not a discrete accelerator chip and not a full SoC.
AI & HPCConsumer ElectronicsIoTView Technology
Arteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
AutomotiveAI & HPCData CenterView Technology
Ambiq SPOT is subthreshold MCU circuit technology, not a wireless protocol stack and not a foundry process.
AI & HPCConsumer ElectronicsMedical+1View Technology
GUC APT is a 2.5D/3D multi-die ASIC packaging-design platform, not a foundry process node and not OSAT assembly.
AI & HPCData CenterTelecommunicationsView Technology
VeriSilicon SiPaaS is a platform-based custom-silicon design and turnkey service, not a foundry process node.
AutomotiveAI & HPCConsumer Electronics+1View Technology
Alchip’s 2nm Design Platform is an ASIC physical-design methodology for 2nm compute dies and chiplet packaging, not a foundry process node.
AI & HPCData CenterTelecommunicationsView Technology
eMemory NeoFuse is anti-fuse embedded OTP/PMTP silicon IP for logic process nodes, not a discrete memory product.
AutomotiveAI & HPCConsumer Electronics+1View Technology
Renesas R-Car is an automotive system-on-chip platform for ADAS, cockpit and vehicle compute, not a standalone data-center accelerator architecture.
AutomotiveAI & HPCView Technology
Synopsys HBM interface IP is a high-bandwidth memory interface family including controller, PHY and verification IP for AI and high-performance computing SoCs. Distinct from UCIe die-to-die IP.
AI & HPCData CenterView Technology
InCore publishes configurable RISC-V processor IP through an automated Core-hub generator that produces synthesizable core instances for custom semiconductor systems.
AI & HPCIndustrialIoTView Technology
Arm Chiplet System Architecture provides standardized system partitioning and connectivity foundations for reusable chiplet-based designs. It is an architecture, not a processor-core catalog.
AutomotiveAI & HPCData CenterView Technology
Cadence design platform for planning, implementing and analyzing 2.5D and 3D multi-die / chiplet systems.
AutomotiveAI & HPCData CenterView Technology
Synopsys die-to-die IP solution for Universal Chiplet Interconnect Express, including controller, PHY and verification IP.
AutomotiveAI & HPCData CenterView Technology
