CONFIGURABLE RISC-V PROCESSOR
Configurable RISC-V processor IP generated from a Core-hub toolchain

Configurable RISC-V processor IP generated from a Core-hub toolchain
ISA and microarchitecture-level configuration described by InCore
AI & HPC · Industrial · IoT
Public source
InCore Semiconductors publishes configurable RISC-V processor IP through its Core-hub generator.
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Illustrative representation based on publicly available technical information.
InCore publishes configurable RISC-V processor IP through an automated Core-hub generator that produces synthesizable core instances for custom semiconductor systems.
Official product pages describe an automated toolchain that lets users configure ISA and microarchitecture choices and produce synthesizable RISC-V core-hub instances with interconnect, uncore and accelerator options. Named core series are presented as configurable processor IP rather than as a catalog of finished chips. InCore also publishes a related SoC Generator for integrating cores into SoC subsystems; this listing identifies the processor-IP platform and does not catalog individual core SKUs. Configuration options, ISA profiles and licensing should be confirmed on InCore's current RISC-V core pages.
Key characteristics associated with this technology.
Configurable RISC-V processor IP generated from a Core-hub toolchain
ISA and microarchitecture-level configuration described by InCore
Processor IP platform, not a catalog of individual named cores
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