
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The PQPlatform-CoPro page reviewed on 12 November 2026 describes a highly flexible cryptographic coprocessor designed to add post-quantum capabilities to an existing security subsystem.
The official page states silicon-proven, configurable PQC acceleration with SCA/FIA protection for ASIC or FPGA under host-CPU firmware control.
Key benefits listed include PQC co-processor with hardware Keccak accelerator; SCA resistance (DPA) and FIA resistance with optional HW for increased performance; flexible architecture supporting both PQC and traditional cryptography; silicon-proven status; quantum-safe security for long-lifecycle products; HW/FW co-design for crypto agility; low power; scalable configurations; and suitability for ASIC or FPGA. Common use cases include secure boot, secure firmware update, device attestation, bulk encryption/hashing acceleration, cryptographic primitives acceleration, TLS/DTLS handshake acceleration, and secure IoT commissioning. The products suite page additionally labels PQPlatform-CoPro as FIPS 140-3 CAVP compliant compact hardware PQC acceleration. Product brief download/evaluation is gated via a form.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Security IP
Security module / crypto IP. Interface controllers and PHYs remain separate listings.
Finder function
Post-quantum crypto coprocessor
Numbered specification: Configurable PQC/traditional crypto CoPro (Hash-only to PQ/T Hybrid per page)
Configurable PQC/traditional crypto CoPro (Hash-only to PQ/T Hybrid per page) is named for this product on the reviewed page.
Numbered specification: FIPS 140-3 CAVP compliance claimed on suite page
FIPS 140-3 CAVP compliance claimed on suite page is named for this product on the reviewed page.
Recorded aliases
PQPlatform-CoPro; PQShield CoPro; PQP-CoPro
Licensable design IP. AES engine for 128-bit blocks and 128-, 192-, or 256-bit keys.
View solutionEnSilica Silicon IP is a licensable portfolio including eSi-Crypto cryptographic accelerators and eSi-ADAS radar processing IP. Official home and Silicon IP pages state silicon-proven blocks with a subset available for external licensing.
View solutionFortifyIQ FortiAES is a family of licensable synthesizable AES IP cores with side-channel and fault-injection resistance. The official catalog page lists hardware AES SKUs and soft-macro, foundry-agnostic delivery.
View solutionIP Cores AES is licensable synthesizable AES (FIPS-197) cipher IP. The official product page states Rijndael encryption/decryption with ECB/CBC/CFB/OFB/CTR modes, 128/192/256-bit keys, and deliverables as Verilog/VHDL source or netlist.
View solutionNoesis ntAES32 is licensable AES (FIPS-197) soft IP. The official product page states encrypt/decrypt of 128-bit blocks with 128/192/256-bit keys, discrete roundkey expansion, and deliverables as synthesizable HDL or FPGA netlist.
View solutionProvenCore is a formally verified microkernel and TEE OS foundation for trusted applications. The official ProvenCore page states GlobalPlatform TEE alignment, Common Criteria / FIPS-oriented certifications, and support for ARM Cortex-A, RISC-V, and hardware accelerators.
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