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Noesis ntAES32 High-Speed AES Cipher IP

The Noesis ntAES32 product page reviewed on 12 November 2026 describes a high-speed AES core implementing NIST FIPS-197 that can encrypt or decrypt 128-bit blocks using 128-, 192-, or 256-bit keys.

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Overview

Noesis ntAES32 is licensable AES (FIPS-197) soft IP.

Hardware roundkey expansion is a discrete building block that can be shared across multiple cores. The page states low latency, high speed, and a simple SoC interface, with targeting to ASIC and FPGA technologies. Deliverables listed include synthesizable VHDL/Verilog or FPGA netlist, testbenches, example configuration files, and a C++ model under an open licensing philosophy with multiple commercial licensing models. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Security IP

    Security module / crypto IP. Interface controllers and PHYs remain separate listings.

  • Finder function

    AES cipher

  • Numbered specification: AES-128/192/256

    AES-128/192/256 is named for this product on the reviewed page.

  • Recorded aliases

    ntAES32; Noesis AES

Lifecycle and categories

Lifecycle stages
Security IP
Solution categories
Cryptography IP
Supported versions
AES-128/192/256
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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