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IP Cores Ultra-Compact AES (FIPS-197) IP

The IP Cores AES product page reviewed on 12 November 2026 describes an ultra-compact Advanced Encryption Standard core implementing Rijndael per NIST FIPS-197, processing 128-bit blocks with 128-bit keys (256-bit key versions available).

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Overview

The official product page states Rijndael encryption/decryption with ECB/CBC/CFB/OFB/CTR modes, 128/192/256-bit keys, and deliverables as Verilog/VHDL source or netlist.

The base encryption-only core is stated at under 3,000 ASIC gates; enhanced versions support encryption and decryption across ECB, CBC, OFB, CFB, and CTR modes with configurable datapath widths and included key expansion. Optional features named include data-integrity parity and DPA-resistance masking/cycle hiding. The design is fully synchronous, self-contained (no external memory), and available as synthesizable Verilog/VHDL or netlist with self-checking testbenches. FIPS-197 AESAVS validation is stated. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Security IP

    Security module / crypto IP. Interface controllers and PHYs remain separate listings.

  • Finder function

    AES cipher

  • Numbered specification: modes ECB/CBC/CFB/OFB/CTR (and related SKUs)

    modes ECB/CBC/CFB/OFB/CTR (and related SKUs) is named for this product on the reviewed page.

  • Recorded aliases

    IP Cores AES1; AES1-8E; IP Cores AES IP

Lifecycle and categories

Lifecycle stages
Security IP
Solution categories
Cryptography IP
Supported versions
AES-128/192/256; modes ECB/CBC/CFB/OFB/CTR (and related SKUs)
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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