Discover 169 technologies from leading innovators around the world.
Arteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
AutomotiveAI & HPCData CenterView Technology
GUC APT is a 2.5D/3D multi-die ASIC packaging-design platform, not a foundry process node and not OSAT assembly.
AI & HPCData CenterTelecommunicationsView Technology
Alchip’s 2nm Design Platform is an ASIC physical-design methodology for 2nm compute dies and chiplet packaging, not a foundry process node.
AI & HPCData CenterTelecommunicationsView Technology
Synopsys HBM interface IP is a high-bandwidth memory interface family including controller, PHY and verification IP for AI and high-performance computing SoCs. Distinct from UCIe die-to-die IP.
AI & HPCData CenterView Technology
Arm Chiplet System Architecture provides standardized system partitioning and connectivity foundations for reusable chiplet-based designs. It is an architecture, not a processor-core catalog.
AutomotiveAI & HPCData CenterView Technology
Cadence design platform for planning, implementing and analyzing 2.5D and 3D multi-die / chiplet systems.
AutomotiveAI & HPCData CenterView Technology
Synopsys die-to-die IP solution for Universal Chiplet Interconnect Express, including controller, PHY and verification IP.
AutomotiveAI & HPCData CenterView Technology
