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Public source

Xylon logiCVC-ML Multilayer Video Controller IP

The Xylon logiCVC-ML product page reviewed on 12 November 2026 describes a Compact Multilayer Video Controller IP core for LCD and other display types on AMD Zynq 7000, UltraScale, and UltraScale+ SoC/FPGA families.

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Overview

Stated features include resolutions up to 8192×8192 including 4K2K@60, up to five layers with configurable size/position/offset, per-layer alpha blending modes (pixel/layer/CLUT), packed pixel formats, multiple output formats (parallel, LVDS, ITU-656), Vivado Design Suite readiness, and OS drivers for Linux and Windows Embedded Compact. Try-before-buy evaluation is offered. Related logicBRICKS include ISP, HDR, JPEG, and camera interface cores. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    Display controller

  • Recorded aliases

    logiCVC-ML; Xylon logiCVC

Lifecycle and categories

Solution categories
Video Codec IP
Supported versions
Up to 4K2K@60 / 8192×8192 stated
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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