
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The intoPIX JPEG XS / TicoXS product page reviewed on 12 November 2026 describes JPEG XS (ISO/IEC 21122) as a lightweight ultra-low-latency mezzanine codec and states that intoPIX co-created the standard.
The official JPEG XS page states ultra-low latency, visually lossless compression and explicitly offers IP cores and software SDKs for licensing.
TicoXS IP cores are described as small-footprint JPEG XS compliant encoders and decoders for FPGA (AMD, Altera, Lattice) and ASIC (examples include TSMC 12/16/28/40 nm), with low power and no external DDR requirement. The page states compression ratios from about 2:1 to 12:1 (and beyond), sub-millisecond/line-based latency, HDR and high bit-depth support, and companion offerings such as TicoXS FIP and FastTicoXS SDKs. Applications named include broadcast ST 2110, AV-over-IP, automotive, displays, and vision. Confirm the exact revision, role, and deliverables on the current provider page before integration.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
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JPEG XS codec
Numbered specification: JPEG XS / TicoXS (High profile
JPEG XS / TicoXS (High profile is named for this product on the reviewed page.
Numbered specification: FIP variant stated separately)
FIP variant stated separately) is named for this product on the reviewed page.
Recorded aliases
TicoXS; intoPIX JPEG XS; TICO-XS
Allegro DVT licenses hardware video encoder and decoder RTL IP covering H.264/HEVC/VP9/AV1/VVC/JPEG and related formats. Official home and Prism E300 Encoder pages state multi-format architectures with RTL source deliverables and AMBA interfaces.
View solutionAlma JPEG-E is licensable Baseline JPEG encoder IP. The official page states ISO/IEC 10918-1 Baseline Sequential DCT compliance with ASIC RTL or FPGA netlist deliverables.
View solutionAtria Logic H.264 UHD Hi422 Intra Encoder is licensable video codec IP. The official site lists High Quality, Low Latency UHD Hi422 60 fps Intra H.264 Codec IP among its multimedia products.
View solutionBitSim FPGA IP Blocks are licensable/reusable imaging and data-acquisition soft IP. The official site states IP blocks for video, graphics, big data, and data acquisition for detector, sensor-interface, and camera products.
View solutionLicensable design IP. H.264 Constrained Baseline encoder with a compressed reference-frame store.
View solutionLicensable H.264 Constrained Baseline decoder IP. It decodes that profile and is not an encoder. Latency, resolution, and frame rate need confirmation.
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