NOV172026
Conference
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Silicon Creations LC-PLL IP
A SerDes or converter reference still needs the specific macro.
- Solution category: Clocking IP
- Offering type: Product
Overview
Silicon Creations LC-PLL IP is a family of LC-tank PLLs aimed at low jitter for analog front ends, converters, PHYs, and RF. An example silicon result does not apply to every family member, and the family is not a serial protocol controller.
Do not treat a best-case jitter number as a family-wide guarantee.
Technical capabilities
Finder function
LC PLL
Configuration checks
Example silicon results do not apply to every macro. Confirm frequency, jitter, and process for the macro you license.
Recorded aliases
lc pll; low jitter pll; serdes reference clock; converter clock
Lifecycle and categories
- Solution categories
- Clocking IP
- Compatibility
- Pricing, licensing, and configuration availability require provider confirmation. Source
Official resources
Related solutions
From the same provider
Silicon Creations Free-Running Oscillator IP
Clocking IPSilicon Creations Free-Running Oscillator IP is a family of on-chip oscillators that need no external resonator. Trimming is available. The provider describes uses such as watchdog timers and MCU core clocks, and quotes best-case accuracy and period jitter that are not a guarantee for every macro. This is not a PLL and it is not crystal-grade accuracy.
View solutionSilicon Creations Ring PLL IP
Clocking IPSilicon Creations Ring PLL IP is a product family of general-purpose fractional-N and specialized ring PLLs. The family page does not state one frequency, jitter, or process that applies to every macro. It is not a PCIe controller. Confirm the exact macro.
View solutionRelated events
NOV192026
Workshop
SystemC Evolution Day 2026
- November 19, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative