Discover 169 technologies from leading innovators around the world.
Metering system-on-chip that Vervesemi describes as an analog front end integrated with a microcontroller for single-phase energy measurement.
IndustrialEnergyView Technology
QuickLogic Australis is embedded FPGA IP, not a standalone FPGA chip and not a foundry process.
AI & HPCIndustrial+2View Technology
Elmos automotive motor-control ICs are mixed-signal BLDC driver chips, parked in Design & IP because Analog / Mixed Signal does not exist.
AutomotiveIndustrialView Technology
CEVA-NeuPro-Nano is edge NPU processor IP, not a discrete accelerator chip and not a full SoC.
AI & HPCConsumer Electronics+1View Technology
Arteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
AutomotiveAI & HPC+1View Technology
Ambiq SPOT is subthreshold MCU circuit technology, not a wireless protocol stack and not a foundry process.
AI & HPCConsumer Electronics+2View Technology
SEALSQ VaultIC is a secure-element chip family, not a software PKI service and not a wireless modem.
AutomotiveIndustrial+2View Technology
GUC APT is a 2.5D/3D multi-die ASIC packaging-design platform, not a foundry process node and not OSAT assembly.
AI & HPCData Center+1View Technology
SG Micro’s analog and mixed-signal platform covers amplifiers, converters and precision analog ICs, parked in Design & IP because Analog / Mixed Signal does not yet exist.
AutomotiveIndustrial+1View Technology
Cirrus Halo Core is the DSP inside Cirrus haptic drivers, parked in Design & IP because Analog / Mixed Signal does not yet exist.
AutomotiveConsumer ElectronicsView Technology
VeriSilicon SiPaaS is a platform-based custom-silicon design and turnkey service, not a foundry process node.
AutomotiveAI & HPC+2View Technology
Alchip’s 2nm Design Platform is an ASIC physical-design methodology for 2nm compute dies and chiplet packaging, not a foundry process node.
AI & HPCData Center+1View Technology
eMemory NeoFuse is anti-fuse embedded OTP/PMTP silicon IP for logic process nodes, not a discrete memory product.
AutomotiveAI & HPC+2View Technology
Texas Instruments analog BCD (LBC) is TI’s bipolar-CMOS-DMOS process identity for foundational analog and power silicon, described in official TI manufacturing communications.
AutomotiveIndustrial+2View Technology
Lattice Nexus is a low-power FPGA platform architecture, not a data-center compute accelerator architecture.
AutomotiveIndustrial+2View Technology
Analog Devices MxFE is a mixed-signal front-end platform that integrates high-speed converters and digital processing for RF sampling systems.
IndustrialTelecommunications+1View Technology
Renesas R-Car is an automotive system-on-chip platform for ADAS, cockpit and vehicle compute, not a standalone data-center accelerator architecture.
AutomotiveAI & HPCView Technology
S32 is NXP’s automotive processing platform: common architecture across vehicle network processors, zonal and real-time controllers, radar and central compute. Official pages emphasize Arm Cortex-A/R/M mix, ASIL D safety, hardware security and TSN Ethernet.
AutomotiveIndustrialView Technology
Microchip PolarFire SoC combines a coherent multi-core RISC-V CPU subsystem with PolarFire FPGA fabric on one device for Linux and real-time embedded systems.
IndustrialMedical+2View Technology
Microchip PolarFire is a mid-range FPGA family providing programmable logic fabric, optional high-speed serial transceivers and on-chip interface IP for communications, imaging and embedded systems.
IndustrialMedical+2View Technology
Synopsys HBM interface IP is a high-bandwidth memory interface family including controller, PHY and verification IP for AI and high-performance computing SoCs. Distinct from UCIe die-to-die IP.
AI & HPCData CenterView Technology
InCore publishes configurable RISC-V processor IP through an automated Core-hub generator that produces synthesizable core instances for custom semiconductor systems.
AI & HPCIndustrial+1View Technology
Mindgrove Secure IoT is a RISC-V-based microcontroller/SoC family for connected and embedded devices, combining a processor core with peripherals, hardware crypto accelerators and on-chip secure memory.
IndustrialConsumer Electronics+1View Technology
Arm Chiplet System Architecture provides standardized system partitioning and connectivity foundations for reusable chiplet-based designs. It is an architecture, not a processor-core catalog.
AutomotiveAI & HPC+1View Technology
