L3 CACHE TILE
L3 cache tile stacked on a CPU core-complex die
L3 cache tile stacked on a CPU core-complex die
Copper-to-copper hybrid bonding with through-silicon vias
AI & HPC · Data Center · Consumer Electronics
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AMD 3D V-Cache is a publicly named 3D packaging technology that stacks an L3 cache tile on a CPU core-complex die.
Silicon Showcase illustrative visual
Illustrative representation based on publicly available technical information.
3D V-Cache stacks an L3 cache tile on a CPU core-complex die using copper-to-copper hybrid bonding and TSVs. Official AMD materials call it the first x86 true 3D die stack, with much higher interconnect density versus 2D chiplets.
Official AMD product-brief materials describe copper-to-copper hybrid bonding and through-silicon vias, presenting the approach as the first x86 true 3D die stack with far higher interconnect density than 2D chiplets or solder-bump 3D stacks. This listing records cache-on-logic hybrid bonding rather than X3D product names as extra rows. Infinity Fabric, listed separately, is the lateral chiplet fabric. Intel Foveros and TSMC SoIC, already in the catalog, are other 3D stacking platforms. Density and cache-size figures should be confirmed on AMD’s current 3D V-Cache documentation.
Key characteristics associated with this technology.
L3 cache tile stacked on a CPU core-complex die
Copper-to-copper hybrid bonding with through-silicon vias
Official materials describe bump-less 3D stacking versus 2D chiplets
Distinct from Infinity Fabric and from Intel Foveros / TSMC SoIC
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