
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Arm documents transformer-network support and configurations from 128 to 2048 MACs.
Embedded NPU for inference, including transformer workloads.
The upper headline is 4 TOP/s at 1 GHz. That headline is an implementation maximum, not measured application performance. Cortex-A and Cortex-M hosts are described as separate processors. Ethos-U85 is an NPU, not a CPU and not an integrated subsystem. Silicon Showcase™ reviewed the page on 2 November 2026. Pricing, license terms, process support, and the exact configuration available for a design are not stated on the reviewed page and require confirmation from the provider.
Published as design IP
Licensable NPU design IP.
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NPU
AONDevices AON1000 is licensable edge-AI IP for always-on voice/sound sensing. The official site lists AON1000/AON1010/AON1020/AONDenoise under Products IP alongside chip and platform offerings.
View solutionBrainChip Akida is licensable neuromorphic neural processor IP. The official IP page describes Akida 1, Akida Pico, and Akida 2 variants with event-based acceleration and IP brochure downloads.
View solutionCEVA-NeuPro-Nano is edge NPU processor IP, not a discrete accelerator chip and not a full SoC.
View solutionA published family of embedded AI processor IP for integration into chips.
View solutionEdgeCortix DNA-II is licensable neural network IP for ASIC, FPGA or SoC. The official DNA page describes run-time reconfigurable interconnects, scalable performance from 1K MACs, and MERA software co-optimization.
View solutionExpedera Origin Evolution NPU IP is licensable AI accelerator IP. The official products overview states packet-based NPU cores scalable from edge devices to data centers with silicon-proven efficiency claims.
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