
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Systemyde International home page reviewed on 12 November 2026 states that the company develops Intellectual Property in the form of synthesizable Verilog HDL models suitable for FPGA, ASIC, or full-custom implementations.
Systemyde Rabbit microprocessor cores are licensable CPU soft IP.
It states the author designed all five generations of Rabbit microprocessors and that a contract with Rabbit Semiconductor gives Systemyde full core rights to these designs. The first three generations are described as completely foundry- and technology-independent, while portions of the last two generations are tied to specific technology/fab because of analog IP. Scope of work claimed includes specification, architecture, Verilog, testbenches, test insertion, and timing closure contributions. Confirm the exact revision, role, and deliverables on the current provider page before integration.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
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Rabbit / embedded CPU
Numbered specification: Rabbit microprocessor generations 1–5
Rabbit microprocessor generations 1–5 is named for this product on the reviewed page.
Recorded aliases
Systemyde Rabbit; Rabbit microprocessor IP
Licensable Armv8-A application CPU IP. Arm's Fixed Virtual Platform guidance documents a Linux software path for Cortex-A class cores. Confirm the OS port for a licensee design.
View solutionLicensable design IP. Cortex-M processor for embedded control, with optional Helium vector processing.
View solutionLicensable design IP. Armv8.1-M Cortex-M processor for embedded control, DSP, and ML workloads.
View solutionBeyond BA2x is a family of licensable 32-bit processor IP cores. The official processors page lists BA20/BA21/BA22/BA25 variants with DMIPS/MHz and area/power figures and a Request a License path.
View solutionMi-V RV32 is the RISC-V soft CPU Microchip recommends for new FPGA designs. The reviewed page lists it for PolarFire SoC, PolarFire, RTG4, SmartFusion 2, and IGLOO 2 FPGAs, with design support in Libero SoC Design Suite. Optional configuration includes compressed instructions, multiply/divide, single-precision floating point, debug, and ECC. It is processor IP for those FPGAs, not portable ASIC CPU IP, and it is not the hardened RISC-V cluster in a PolarFire SoC device.
View solutionWDC W65C02 IP is licensable 65xx CPU soft/firm IP. The official site lists Intellectual Property among products, including W65C02SOC HDL SoC design materials for ASIC/FPGA use.
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