
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The official technology page labels REDEFINE Soft IP as licensable drop-in accelerator IP.
The provider describes a runtime-reconfigurable compute fabric for AI, telecom, HPC, and edge workloads. It is not the MuDRA test chip, not a finished accelerator card, and not a CPU or NPU core.
A separate MuDRA test chip is described as silicon validation of that IP on 28 nm TSMC, with a test chip targeted for Q3 2026 and a commercial-grade MuDRA targeted for Q4 2027. Those dates and the test chip are not this listing. Configuration, process portability, and licensing terms need confirmation with Morphing Machines.
AONDevices AON1000 is licensable edge-AI IP for always-on voice/sound sensing. The official site lists AON1000/AON1010/AON1020/AONDenoise under Products IP alongside chip and platform offerings.
View solutionAllegro DVT licenses hardware video encoder and decoder RTL IP covering H.264/HEVC/VP9/AV1/VVC/JPEG and related formats. Official home and Prism E300 Encoder pages state multi-format architectures with RTL source deliverables and AMBA interfaces.
View solutionAlma JPEG-E is licensable Baseline JPEG encoder IP. The official page states ISO/IEC 10918-1 Baseline Sequential DCT compliance with ASIC RTL or FPGA netlist deliverables.
View solutionLicensable Armv8-A application CPU IP. Arm's Fixed Virtual Platform guidance documents a Linux software path for Cortex-A class cores. Confirm the OS port for a licensee design.
View solutionLicensable design IP. Cortex-M processor for embedded control, with optional Helium vector processing.
View solutionLicensable design IP. Armv8.1-M Cortex-M processor for embedded control, DSP, and ML workloads.
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