Emerging Signal
Vertically stacked complementary transistors are extending logic scaling beyond conventional gate-all-around architectures.
A complementary FET stacks n-type and p-type transistors vertically instead of placing them side by side. Device research treats this architecture as a candidate for continuing logic-cell scaling after gate-all-around nanosheet transistors. Two integration paths are under study: building the stack in one process flow, or forming the upper device on a transferred layer.
Side-by-side n-type and p-type devices set a limit on how short a standard cell can be. Vertical stacking is being explored because it can take that separation out of the cell height. The tradeoff is a more complex process, including new ways to contact each device.
Watch how monolithic and sequential integration approaches develop, how the stacked devices are contacted and powered, and which channel materials are evaluated for the upper and lower transistors.
imec · Primary
Complementary FET (CFET) on the logic technology roadmap
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Chip scaling roadmap
Visit source (opens in a new tab)Technology Signals are editorial summaries based on publicly available sources. Technical claims remain attributable to their original sources.
