Discover 169 technologies from leading innovators around the world.
QuickLogic Australis is embedded FPGA IP, not a standalone FPGA chip and not a foundry process.
AI & HPCIndustrialAerospace & Defense+1View Technology
CEVA-NeuPro-Nano is edge NPU processor IP, not a discrete accelerator chip and not a full SoC.
AI & HPCConsumer ElectronicsIoTView Technology
Arteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
AutomotiveAI & HPCData CenterView Technology
Ambiq SPOT is subthreshold MCU circuit technology, not a wireless protocol stack and not a foundry process.
AI & HPCConsumer ElectronicsMedical+1View Technology
Cirrus Halo Core is the DSP inside Cirrus haptic drivers, parked in Design & IP because Analog / Mixed Signal does not yet exist.
AutomotiveConsumer ElectronicsView Technology
Texas Instruments analog BCD (LBC) is TI’s bipolar-CMOS-DMOS process identity for foundational analog and power silicon, described in official TI manufacturing communications.
AutomotiveIndustrialConsumer Electronics+1View Technology
Lattice Nexus is a low-power FPGA platform architecture, not a data-center compute accelerator architecture.
AutomotiveIndustrialConsumer Electronics+1View Technology
Analog Devices MxFE is a mixed-signal front-end platform that integrates high-speed converters and digital processing for RF sampling systems.
IndustrialTelecommunicationsAerospace & DefenseView Technology
Microchip PolarFire SoC combines a coherent multi-core RISC-V CPU subsystem with PolarFire FPGA fabric on one device for Linux and real-time embedded systems.
IndustrialMedicalAerospace & Defense+1View Technology
Microchip PolarFire is a mid-range FPGA family providing programmable logic fabric, optional high-speed serial transceivers and on-chip interface IP for communications, imaging and embedded systems.
IndustrialMedicalTelecommunications+1View Technology
Synopsys HBM interface IP is a high-bandwidth memory interface family including controller, PHY and verification IP for AI and high-performance computing SoCs. Distinct from UCIe die-to-die IP.
AI & HPCData CenterView Technology
Cadence design platform for planning, implementing and analyzing 2.5D and 3D multi-die / chiplet systems.
AutomotiveAI & HPCData CenterView Technology
Synopsys die-to-die IP solution for Universal Chiplet Interconnect Express, including controller, PHY and verification IP.
AutomotiveAI & HPCData CenterView Technology
