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2.5D chiplet assembly on silicon interposer or redistribution-layer fan-out (Foveros-S and Foveros-R)
2.5D chiplet assembly on silicon interposer or redistribution-layer fan-out (Foveros-S and Foveros-R)
3D stacking with copper-to-copper hybrid bonding (Foveros Direct 3D)
AI & HPC · Data Center · Consumer Electronics
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Intel Foveros is a family of advanced packaging technologies used to place and interconnect multiple dies in one package.
Official technology image
Intel Foundry 3D stacking and 2.5D chiplet packaging family, including hybrid-bonding options described as Foveros Direct 3D. EMIB is a separate 2.5D bridge platform.
Public Intel Foundry pages describe Foveros-S 2.5D assembly on a silicon interposer, Foveros-R 2.5D using redistribution-layer fan-out, and Foveros Direct 3D, which uses copper-to-copper hybrid bonding for vertical stacking. Those named Foveros variants remain capabilities of this family rather than separate listings. Intel also notes compatibility with chiplet interconnect approaches such as UCIe. EMIB, a silicon-bridge 2.5D interconnect described on the same Foundry packaging pages, is listed independently. Process options, design rules and current availability should be confirmed on Intel’s official packaging pages.
Key characteristics associated with this technology.
2.5D chiplet assembly on silicon interposer or redistribution-layer fan-out (Foveros-S and Foveros-R)
3D stacking with copper-to-copper hybrid bonding (Foveros Direct 3D)
Described as compatible with chiplet interconnect approaches such as UCIe
Distinct from Intel EMIB, which is a separate 2.5D embedded-bridge platform
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