
NOV172026
Conference
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Microsoft documents Azure NetApp Files as file storage for electronic design automation workloads such as chip design validation and tape-out.
It does not include EDA tool licenses or a license to Microsoft chip architectures. The published AI Inference Silicon signal stays a separate record. Confirm region, capacity, and which EDA tools are licensed separately.
Availability
Listed by the provider. Confirm the configuration before use.
Cloud compute and storage infrastructure for electronic design automation workloads.
View solutionCloud infrastructure for semiconductor design and verification workloads.
View solution
