Discover 169 technologies from leading innovators around the world.
Elmos automotive motor-control ICs are mixed-signal BLDC driver chips, parked in Design & IP because Analog / Mixed Signal does not exist.
AutomotiveIndustrialView Technology
Arteris FlexNoC is on-chip network IP, not a packaged interconnect chip and not a coherent cache controller.
AutomotiveAI & HPC+1View Technology
SEALSQ VaultIC is a secure-element chip family, not a software PKI service and not a wireless modem.
AutomotiveIndustrial+2View Technology
SG Micro’s analog and mixed-signal platform covers amplifiers, converters and precision analog ICs, parked in Design & IP because Analog / Mixed Signal does not yet exist.
AutomotiveIndustrial+1View Technology
Cirrus Halo Core is the DSP inside Cirrus haptic drivers, parked in Design & IP because Analog / Mixed Signal does not yet exist.
AutomotiveConsumer ElectronicsView Technology
VeriSilicon SiPaaS is a platform-based custom-silicon design and turnkey service, not a foundry process node.
AutomotiveAI & HPC+2View Technology
eMemory NeoFuse is anti-fuse embedded OTP/PMTP silicon IP for logic process nodes, not a discrete memory product.
AutomotiveAI & HPC+2View Technology
Texas Instruments analog BCD (LBC) is TI’s bipolar-CMOS-DMOS process identity for foundational analog and power silicon, described in official TI manufacturing communications.
AutomotiveIndustrial+2View Technology
Lattice Nexus is a low-power FPGA platform architecture, not a data-center compute accelerator architecture.
AutomotiveIndustrial+2View Technology
Renesas R-Car is an automotive system-on-chip platform for ADAS, cockpit and vehicle compute, not a standalone data-center accelerator architecture.
AutomotiveAI & HPCView Technology
S32 is NXP’s automotive processing platform: common architecture across vehicle network processors, zonal and real-time controllers, radar and central compute. Official pages emphasize Arm Cortex-A/R/M mix, ASIL D safety, hardware security and TSN Ethernet.
AutomotiveIndustrialView Technology
Arm Chiplet System Architecture provides standardized system partitioning and connectivity foundations for reusable chiplet-based designs. It is an architecture, not a processor-core catalog.
AutomotiveAI & HPC+1View Technology
Cadence design platform for planning, implementing and analyzing 2.5D and 3D multi-die / chiplet systems.
AutomotiveAI & HPC+1View Technology
Synopsys die-to-die IP solution for Universal Chiplet Interconnect Express, including controller, PHY and verification IP.
AutomotiveAI & HPC+1View Technology
